The Chinese University of Hong Kong
Department of Computer Science and Engineering


Title: Self-Test for State-of-the-art VLSI Designs
Date: August 25, 2009 (Tuesday)
Time: 11:00 a.m. - 12:00 noon
Venue: Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
Shatin, N.T.
Speaker: Professor Alex Orailoglu
Department of Computer Science and Engineering
University of California, San Diego


Design for test methodologies, particularly Built-in Self-test (BIST), are playing an increasingly significant role in managing the test cost of current designs. To reap the significant cost reduction benefits of BIST in test generation and test application, possible deterioration in terms of fault coverage levels and diagnostic capabilities, due to random resistant faults and limited response information, needs to be averted.

We outline initially an investigation of on-chip pseudo-random test pattern generators and of methodologies for selection of suitable pattern generators for VLSI designs. We follow this up with a study of methodologies for reducing the cost of deterministic test pattern application. On the fault diagnosis side, efficient fault diagnosis approaches are proposed for scan-based BIST designs. Improvements in information extraction from the BIST signature are attained through utilization of both superior deterministic partitioning schemes and enhanced analysis procedures. The talk continues with an investigation of concurrent test for linear digital systems. A low-cost, accumulation based concurrent error detection scheme provides considerable benefits through observation of the average behavior of the system and through careful gate level fault effect consideration. The significant benefits provided by the techniques proposed are attained at negligible hardware costs, ensuring the continued dominance of on-chip test techniques for state-of-the-art VLSI designs.


Alex Orailoglu is a professor of computer science and engineering at the University of California, San Diego. His research interests include embedded systems and processors, digital and analog test, fault-tolerant computing, CAD, and nanoelectronics. He has an SB in applied mathematics from Harvard University, and an MS and a PhD in computer science from the University of Illinois at Urbana-Champaign. He is a Golden Core member of the IEEE Computer Society.

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