|Title:||Timing Driven Physical Synthesis and Clock Network Synthesis in IBM|
August 27, 2009 (Thursday)
2:30 p.m. - 3:30 p.m.
Room 1021, 10/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
Dr. Cliff Sze
IBM Austin Research Laboratory
In order to continue the Moore's law, VLSI technology is scaling down into 45nm/32nm/22nm regime and scaling out to multi-core architectures. Global and local wire delays become the dominant factor in delay optimization and create new challenges for existing physical synthesis tools. Coupled with conflicting optimization objectives such as delay, area, power and wireability, the timing closure problem of complex VLSI design becomes almost intractable and leads to severe time-to-market problems. In this presentation, we will go over IBM fast timing closure flow which has shown success in this area. If time permits, the topics would includes wire Synthesis, buffer insertion, gate cloning, local placement refinement, congestion reduction, all of which has been proved to be very effective for IBM timing closure flow.
The talk would also include a brief introduction on different EDA research in IBM Austin Research Laboratory and the clock network synthesis contest which is organized by International Symposium on Physical Design sponsored by ACM/SIGDA and IEEE/CAS.
Cliff Sze received the B.Eng. and M.Phil. degrees from the Department of Computer Science and Engineering, the Chinese University of Hong Kong and the Ph.D. degree in computer engineering at the Department of Electrical Engineering, Texas A&M University. Since 2005, he has been with IBM Austin Research Laboratory, Austin, Texas, where he focuses on integrated placement and timing optimization for ASIC and microprocessor designs. Cliff has contributed to several IBM ASIC designs, as well as POWER 6, POWER 7, Xbox 360 and the Sony/Toshiba/IBM CELL processors. He received several IBM technical/invention awards, filed 13 patents applications and was granted 2 patents. His research interests include design and analysis of algorithms, computer-aided design technique for very large scale integration, physical design, and performance-driven interconnect synthesis.
Dr. Cliff Sze has been actively serving the academic/research community, for example, on the program committees for ICCAD, ASPDAC, SLIP, SOCC, and as reviewer for IEEE Transactions on Computer-Aided Design as well as IEEE Transactions on Circuits and Systems. He also has served as a mentor for several SRC projects. Currently, he serves as the chair of the clock network synthesis contest in ACM/IEEE International Symposium on Physical Design. Dr. Sze was the recipient of the IEEE/ACM Design Automation Conference Graduate Scholarships.
Enquiries: Miss Temmy So at tel 2609 8444
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar